WinUAE: Due nuove beta uscite in 24 ore che fixano e migliorano l'emulazione, tra le novità il fix sul problema da me segnatato a Toni Wilen riguardo la configurazione HD Controller CDTV SCSI, in allegato le citazioni delle 2 ultime beta.
WinUAE 4.0.0 Beta 5 : Download
WinUAE 4.0.0 Beta 5 (64Bit): Download
Beta 4:
- Show only every 10th frame in D3D11 warp mode. For some reason Present() blocks if rate is higher than current max monitor refresh rate, not even DXGI_PRESENT_ALLOW_TEARING or DXGI_PRESENT_DO_NOT_WAIT help.
- Normal windowed D3D11 vsync mode should work correctly again.
- Default WASAPI audio device now follows Windows default audio device if default gets changed and emulation is already running.
- Renamed new low latency vsync to official "Lagless VSYNC (Beamraced)".
- Flip first slice early, before vblank (Early flip won't cause tearing as long as it happens during last slice). This should fix tearing in topmost slice when flip gets delayed (which for some unknown reason seems to regularly happen if flipping is done during vblank). This change makes last debug color bar shorter which is normal.
- Use NtDelayExecution and ZwSetTimerResolution (if available) for sub 1ms delays in non-fastest possible CPU low latency vsync modes.
- Replaced FastLane ROM with full 32k dump.
- Emulated (partially) C-Ltd Kronos.
- Removed CDTV SCSI from Advanced Chipset. It is optional hardware module and should be only in Expansion panel. Old CDTV SCSI configured config files are still supported but this and future versions won't write old CDTV SCSI config file entry to config file anymore.
C-Ltd Kronos:
- 5380 based SCSI controller with buffer RAM.
- Boot ROM added ("CLtd RomBoot 3.4, Copyright 1989, Wayne E. Miller")
- Boot ROM is only small driver loader from drive's custom partition table.
- SCSI settings are stored in 256 bit 93C06 serial EEPROM. EEPROM is emulated but data is static (boot enabled, SCSI ID=7)
- Install disk is MIA: Emulation is not yet complete, for example buffer RAM/fake DMA is not emulated.
Beta 5:
- Single scan line off by one fix in lagless vsync, frames+ mode now works correctly without static horizontal lines.
- Single slice lagless vsync had blank display (b4)
- Automatic scaling and some other scaling modes had very strange corrupted display in lagless vsync mode. Some small tearing is still possible if scaling is large enough.
- END+F9 lagless vsync debug mode now also adds small flickering markers that show where Amiga-side slices are positioned (Optimally they should be in the middle of large color bars). Switching screen modes does not anymore automatically disable debug colors.
- Reduced amount of data copied in lagless vsync if null filter or d3d shader is enabled.
- Overlay leds (b2) are now also supported in D3D9 mode.
- BPLCON1 delay logic fix when single scanline had at least one odd plane delay not equaling even plane delay and then one or more odd == even delays. (Very rare situation)
- Debugger fa command didn't find anything.
- Disassembler crashed if it disassembled FMOVECR instruction and statefile was loaded without enabled FPU.
- Switching from non-cycle exact to cycle exact mode stopped interrupts if only single INTENA interrupt was enabled.
- Moved CDTV SRAM from Advanced chipset to Expansions and added size selection.
Lagless vsync is now mostly complete. Tweaking to do, depending on feedback.
